The present invention relates to an apparatus for the conversion of IEEE standard floating-point numbers into two's complement format floating-point numbers or vice versa.
A numerical value or data used in scientific or technical calculation is expressed in a floating-point number consisting of an exponent e and a mantissa m. A numerical value f having a base b can be represented by Equation (1) below. EQU f=m.times.b.sup.e ( 1)
Equation (1) permits the expression of a wide range of numerical values in a limited number of bits.
A typical floating-point format is the standard format proposed by the Institute of Electrical and Electronics Engineers (IEEE). This format is used in many microcomputers. The 32-bit floating-point format standardized by IEEE has the following features. As illustrated in FIG. 1, the format consists of a sign bit S, an eight-bit exponent E and a 23-bit mantissa M. The exponent is expressed in a biased form, wherein 127 is added to the real value of the exponent, and the mantissa is expressed in its absolute value and can represent a number within the range of Equation (2). EQU 1.ltoreq.f&lt;2 (2)
Since, however, the most significant bit (MSB) of the normalized number is always "1", the MSB is omitted, and the number is expressed from the second most significant bit on.
The case in which the value of the exponent is at its maximum, 127, is specially treated as a non-number, and the case in which the value of the exponent is at its minimum, 0, is exceptionally treated as a denormalized number. For further details, reference may be made to "A Proposed Standard for Binary Floating-Point Arithmetic", Draft 8.0 of IEEE Task P754, 1981.
Along with the IEEE standard format referred to above, there is also used a floating-point format, in which both the exponent and the mantissa are expressed in two's complement representation.
For instance, a floating-point arithmetic processor manufactured by TWR LSI Products uses floating-point numbers using the two's complement format. For details on this format, reference may be made to John A. Eldon et al., "A Floating-Point Format for Signal Processing", Proceedings of the 1982 IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 717-720. Whereas the article proposes a 22-bit floating-point format, the 22 bits consist of six exponent bits and 16 mantissa bits, there can also be conceived, as an expansion of the 22-bit format, a 32-bit floating-point format using an eight-bit exponent and a 24-bit mantissa, both expressed in two's complement representation, as shown in FIG. 2. This shall hereinafter be called the two's complement 32-bit floating-point format.
However, when data processed in the two's complement 32-bit floating-point format are to be used by a computer conforming to the IEEE standard format or vice versa, conversion is required between the two different formats of expression. Though the format conversion may be achieved by a program combining bit processing and arithmetic processing, it would entail the problem of requiring a large number of steps.